In certain preferred embodiments of commonly assigned U.S. Pat. No. 5,861,666, the disclosure of which is hereby incorporated by reference herein, a stacked microelectronic assembly includes a plurality of chip and interposer subassemblies. Each subassembly has a circuitized interposer and a semiconductor chip, one face of which confronts a surface of the interposer. Each interposer has at least one peripheral region projecting laterally beyond an edge of the chip mounted to the interposer. Each interposer also includes a plurality of leads electrically connected to contacts on the chip face that extend to the peripheral region of the interposer. The subassemblies are stacked one atop another in a generally vertical configuration so that the chips overlie one another and so that the projecting portions of the interposers overlie one another. The subassemblies are electrically connected one to another by vertical conductors extending alongside the chips and interconnecting the leads of the various interposers at their peripheral regions.
FIG. 1A shows a microelectronic assembly 100 disclosed in U.S. Pat. No. 5,861,666 made from a number N of prefabricated subassemblies, comprising N−1 subassemblies 110 and base subassembly 120. Subassembly 110 comprises a semiconductor chip 101 having opposed surfaces 102 and 103, one surface having exposed electrical contacts (not shown), and an interposer 115 having a first surface 116 and a second surface 117. Interposer 115 is preferably a flexible sheet-like element. Chip 101 is mounted on first surface 116 of interposer 115 and the contacts are electrically connected to conductors (not shown) on a surface of interposer 115. Fan-out connectors 111, such as high-melting temperature solder balls, are affixed to the second surface 117 of the interposer 115 (the side opposite chip 101). In each subassembly 110, the electrical connections between chip 101 and interposer 115 are encapsulated in a material 104 such as an epoxy or elastomer, which fills the gaps between chip 101 and surface 116 and partially surrounds the chip. The base subassembly 120 comprises an encapsulated microelectronic element 101, encapsulant 104 and interposer 125 similar to those described above for subassembly 110. A plurality of joining units 121 are affixed to second surface 127 (the side opposite from microelectronic element 101) of interposer 125. Base subassembly 120 is adapted to serve as the bottom-most unit of stack 100 and may be affixed directly to an external element such as a printed circuit board or a second microelectronic assembly.
When subassemblies 110 and 120 are stacked, fan-out connectors 111 electrically interconnect the subassemblies within the stack, thereby acting as vertical conductors. To allow stacking, fan-out connectors 111 of each subassembly 110 must be positioned outside of the region of interposer 115 of the next lower subassembly occupied by chip 101 and encapsulant 104. Typically, this requirement results in fan-out connectors 111 of each subassembly 110 being disposed in a peripheral region of interposer 115 which is not covered by encapsulant 104 on first surface 116. This peripheral region, therefore, remains quite flexible, which may lead to difficulties in handling the subassemblies and in bonding the fan-out connectors when the subassemblies are stacked. The subassemblies can be made more rigid by dispensing additional encapsulant as shown in FIG. 2A. Increasing the area covered by encapsulant reduces the area available for the fan-out connectors, thereby decreasing the number of rows of connectors that may be used and resulting in poor utilization of the interposer. The problems arising from excessive flexing of the peripheral regions are even more pronounced where multiple rows of fan-out connectors or joining units are employed (FIG. 2B) and where a differently sized die is used in the upper subassemblies (FIG. 2C).
In spite of the advances set forth in U.S. Pat. No. 5,861,666, there remains a need for a stackable microelectronic subassembly that is easily handled and tested during making of a stacked microelectronic assembly. There also remains a need for a stackable microelectronic subassembly having a stiffening layer for stiffening peripheral regions of the subassembly. The present invention addresses these needs.